Substantial improvements in graphics hardware combined with standardized graphics languages have allowed the use of complex graphics functions in many common applications. As these applications increase, more and more graphics functionality are moved from the central processing unit to the hardware graphics pipeline in a computer graphics system. Thus, the hardware graphics pipeline is now able to perform many functions so as to not slow down the performance of the computer graphics system.
Many prior art computer graphic systems are implemented with a host processor constructing and generating a display list of commands comprising graphics opcode commands and parameters which are sent to a hardware graphics pipeline. The hardware graphics pipeline takes the list of commands, or “display list” and creates or generates graphics primitives for a display device. These graphics primitives are constructed into graphics images displayed on the display device. The graphics primitives typically include points, lines, and polygons representing graphics objects rendered by the graphics processor.
Prior Art FIG. 1 illustrates a computer graphics system 100, in accordance with the prior art. The computer graphics system 100 includes one or more processors, such as processor 102, which is connected to a main memory 104. The computer graphics system 100 also includes a hardware graphics pipeline 106.
In use, a display list for the hardware graphics pipeline 106 may be supplied in series to be processed by the hardware graphics pipeline 106 by reading the display list data from linear memory locations in the main memory 104. The main memory 104 may thus include a plurality of buffers 108 with opcode commands and parameters to be carried out.
The hardware graphics pipeline 106 may be equipped with a direct memory access (DMA) module 110 for sequencing through the buffers 108 of the main memory 104.
Thus, per the foregoing display list processing method, display list commands are received sequentially into the main memory 104 in a linear array of memory locations. After some temporal period, such commands are read from the linear array of memory locations in the main memory 104. Inherent with this method is a temporal period between a time when the commands are received into the main memory 104 and executed by the hardware graphics pipeline 106.
Due to this temporal period, the hardware graphics pipeline 106 unfortunately can not rely on the processor 102 for aid during the processing of such commands. Conversely, the processor 102 can not easily manage the graphics processing being executed on the hardware graphics pipeline 106. This problem has particular ramifications during one specific type of graphics processing, namely occlusion processing. An example of such occlusion processing and how the present problem affects the same will now be set forth.
Prior Art FIG. 2 illustrates an example of graphics processing that may be carried out utilizing the computer graphics system 100 of FIG. 1, and a particular problem associated therewith. As shown, a truck 200 to be rendered is provided along with various portions 204. One of such portions 204, the engine 206, is graphically intense since it has a lot of detail to be rendered.
One common method of parsing such rendering and reducing the overall work to be performed by the hardware graphics pipeline 106 entails enclosing each of the various portions 204 with bounding volumes 208. By enclosing certain portions 204 such as the engine 206, the hardware graphics pipeline 106 may perform tests (i.e. z-value, stencil, etc.) to determine whether the particular portion 204 (i.e. the engine 206) needs to be drawn (i.e. is lid 210 closed or open). Based on such tests, it may be determined whether each of the portions 204 is visible and must be drawn.
To this end, significant work may be avoided by conditionally processing various portions 204 in the hardware graphics pipeline 106 based on the results of the foregoing tests. Unfortunately, in the computer graphics system 100 of FIG. 1, the results of the foregoing tests must be sent to the processor 102 for the decision as to whether to draw the portions 204. Thus, the occlusion tests are only effective when the processor 102 is involved in drawing the current frame, due to the latency incurred by the aforementioned temporal period. Moreover, the processor 102 often sends all of the drawing primitives of a frame before the hardware graphics pipeline 106 even begins processing the primitives.